The present invention relates to an information processing apparatus and a method for accelerating information processing thereof.
In an information processing apparatus, a condition code indicating a state of an operation result is generated each time an instruction is executed. The generated condition code is used for determination at a conditional branch instruction or a conditional instruction. An example related to a related method for controlling the condition code is described in Japanese Patent Laid-Open No. 8-305563.
In the condition code control described in the Laid-Open No. 8-305563, the condition code is generated each time the instruction is executed. The conditional instruction, in which an operation is executed when a specified condition is satisfied, includes a condition specification field for indicating the specified condition. It is determined whether or not the condition code matches the condition specified in the condition specification field, and only when the condition code matches the condition, the conditional instruction is executed.
In the related method, the condition code is often generated whenever each operation instruction is executed. However, the condition code is not necessarily always used, and an instruction in which the condition code is used is limited to the above described conditional instruction, the conditional branch instruction and the like. Depending on an implementation of a processor or a processor emulation method, a condition code generation process may take more time than the determination of the condition code. It means that it takes time to generate an unnecessary condition code. Moreover, since the above described conditional instruction is the instruction dedicated to the information processing apparatus thereof, it is difficult to maintain compatibility with other software or microinstructions.
Moreover, in Japanese Patent Laid-Open No. 10-69384 and Japanese Patent Laid-Open No. 11-327901, in association with a delayed branch control method for controlling a branch operation of a delayed branch instruction in a processor of a delayed branch method, a condition flag rewriting control method for controlling rewriting of a condition flag is disclosed. In the condition flag rewriting control method, whether the rewriting of the condition flag is allowed or disallowed is controlled based on the order of instructions.
In Japanese Patent Laid-Open No. 57-5152, a technique related to a read control method of a storage device is disclosed. The method includes the storage device, an address register having a counting function, means for creating a next block number address, and means for storing a branch address. The storage device stores a micro program. The address register having the counting function connects directly to the storage device. When a microinstruction word is serially read out from the storage device, the address register having the counting function counts up the address stored in the address register, and the means for creating the next block number address creates the next block number address. The means for storing the branch address stores the branch address included in the microinstruction word read out from the storage device when a branch process is performed, in the address register having the counting function.
In Japanese Patent Laid-Open No. 2003-99248, a technique related to a control function for a processor including instruction supply means, interpreter means, instruction issuing control means, and execution means is disclosed. The instruction supply means supplies multiple instructions, and the interpreter means interprets the multiple instructions respectively. Execution condition information for specifying conditions indicating whether or not the respective instructions are executed is specified in the multiple instructions, and with reference to the conditions specified in the execution condition information, the instruction issuing control means determines an instruction or a set of instructions which executes a valid operation. Operations of the respective instructions are specified in the multiple instructions, and based on the specification, the execution means executes one or more operations. The instruction issuing control means further has the following functions. First, the instruction issuing control means determines whether the instruction is a valid instruction which is required to be executed or an invalid instruction which is not required to be executed, by referring to the conditions specified in the execution condition information. With respect to the instruction determined as the invalid instruction, the instruction issuing control means controls to delete the instruction itself before issuing the instruction to the execution means. Then, instead of the deleted instruction, the instruction issuing control means controls to issue a subsequent valid instruction to the execution means.